Senior/Staff ASIC Design Engineer

Senior/Staff ASIC Design Engineer Opportunity - Munich - Global Semis Company!

A rapidly growing global semiconductor industry player specialising in digital & mixed-signal battery and power management solutions is seeking an experienced Senior/Staff ASIC Design Engineer to join their team!

Key Skills Needed:

1. Experience in RTL Design for complex ASIC projects.
2. Experience working on full-flow projects.
3. Exposure to multiple elements of the ASIC design cycle, including: specification definition, RTL coding, synthesis, ATPG generation or verification.
4. Proficient in at least one hardware description language (e.g., Verilog or SystemVerilog).
5. Involvement in at least one successful tape-out.

If you are interested in finding out more or applying for this role, please contact Lucy Edmondson.