Verification Engineer - languages SV and UVM methodology - Contract
Posted 5 days 2 hours ago by Silicon Logic
Location: Manchester Or Sheffield
Key Responsibilities: Requirements :
JOB DESCRIPTION
Experienced Verification Engineer with:
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Minimum of 5+ years of relevant experience at IP level verification
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Expertise in verification languages in particular SV and UVM methodology
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Available to work on long-term contract (at least one year)
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A good listener who will gain a clear knowledge of what is required and is not afraid to ask anyquestions in order to gain that understanding
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An efficient worker who has a proactive approach towards on-time delivery
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Ability to work with other experts to solve complex problems
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Aptitude for clear communication of issues and progress. Be prepared to give and take
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help where necessary to keep work on target and to share knowledge with other team members