Design Verification Engineer 2

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting-edge technology that changes our world. Microsoft's Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.

We are looking for a Design Verification Engineer to work in the dynamic Microsoft Artificial Intelligence Silicon Engineering team (AISiE). The candidate must be a highly motivated self-starter who will thrive in this cutting-edge technical environment.

Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

Qualifications

• 7 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IPs
• 2 or more years of experience with ATE/ATM vector generation and vector verification for Post Si Production Testing
• Experience with JTAG/TAP debug interfaces
• In-depth knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments.
• Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
• Scripting language such as Python or Perl or Tcl/Tk
• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Responsibilities

The AISoC silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.

• Plan the SoC level verification of IP/Subsystem interacting with design engineers to identify verification test scenarios.
• Familiar with the constrained-random verification environments using SystemVerilog and UVM, and able to enhance & develop the verification component of the testbench.
• Execute the IP/Subsystem SoC level verification plan
• Analyse and debug test failures with designers to deliver functionally correct design.
• Identify and write functional coverage for stimulus and corner cases.
• Close coverage to plug verification holes and meet tape out requirements.
• Work with the partner IP/SS dv teams to identify and run the ATM and ATE test vectors in SoC environment.
• Write scripts to convert the test vector patterns into format defined by Product Engineering (PE) team.
• Work with the product engineering teams on the delivery of manufacturing test patterns.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.