Verification Engineer - System Verilog, RTL

My client is currently looking for a verification engineer for a long term contract.

• Experienced verification engineer who knows tools (Cadence) and RTL language (System Verilog) very well
• Strong expertise in Python language as our reference models are written in Python
• His/her main work would be to match the behavior of the RTL model with the Python model for various blocks
• UVM knowledge is not necessary, but if you have some it does not hurt

If this looks of interest then send your CV now and call for more information. This role will be remote with only a need to go onsite to start for the first week or so.