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Verification Engineer - languages SV and UVM methodology - Contract

Posted 5 days 2 hours ago by Silicon Logic

Contract
Not Specified
Other
Lancashire, Manchester, United Kingdom, M21 0
Job Description

Location: Manchester Or Sheffield

Key Responsibilities: Requirements :

JOB DESCRIPTION

Experienced Verification Engineer with:

  • Minimum of 5+ years of relevant experience at IP level verification

  • Expertise in verification languages in particular SV and UVM methodology

  • Available to work on long-term contract (at least one year)

  • A good listener who will gain a clear knowledge of what is required and is not afraid to ask anyquestions in order to gain that understanding

  • An efficient worker who has a proactive approach towards on-time delivery

  • Ability to work with other experts to solve complex problems

  • Aptitude for clear communication of issues and progress. Be prepared to give and take

  • help where necessary to keep work on target and to share knowledge with other team members

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